1. Field of the Invention
The present invention relates to a layered chip package that includes a plurality of semiconductor chips stacked, and to a method of manufacturing the same.
2. Description of the Related Art
In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation. The through electrode method is free from the above-mentioned problems of the wire bonding method.
U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In the method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip have their respective end faces exposed in a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed in the same side surface of the stack.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.
U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of electrically-conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated from each other into individual multilayer modules.
The yield of chips from a wafer that is to be cut later into a plurality of chips, i.e., the ratio of the number of conforming chips to the total number of chips in the wafer, is generally 90% to 99%. A layered chip package includes a plurality of chips. Therefore, the possibility that all the chips included in a layered chip package are conforming is lower than the yield of the chips. As the number of chips included in a layered chip package increases, the possibility that all the chips included in the layered chip package are conforming decreases.
A case will now be considered where a memory device such as a flash memory is constructed using a layered chip package. Generally, in a memory device such as a flash memory, a redundancy technique to replace a defective column of memory cells with a redundant column of memory cells is used so that the memory device can operate normally even when some memory cells are defective. Also in a memory device constructed using a layered chip package, if some of a plurality of memory cells included in a chip are defective, the redundancy technique can be used to allow the memory device to operate normally while allowing the use of the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells becomes defective due to, for example, a wiring failure in the control circuit, and even the redundancy technique cannot allow the chip to operate normally. In such a case, the defective chip is no longer usable. One possible solution to this case is to replace the defective chip with a conforming chip. However, this increases the manufacturing cost of the layered chip package.
Another possible solution is that a plurality of layered chip packages each including no defective chips are electrically connected to each other to construct a memory device including a desired number of chips. In this case, however, there is a problem that the wiring for electrically connecting the plurality of layered chip packages to each other becomes complicated.
U.S. Pat. No. 7,745,259 B2 discloses a layered chip package having a configuration as described below. The layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each of the plurality of layer portions includes a semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The wiring is connected to the plurality of electrodes, the plurality of first terminals, and the plurality of second terminals of the plurality of layer portions. A plurality of such layered chip packages can be stacked on each other and electrically connected to each other.
In the layered chip package disclosed in U.S. Pat. No. 7,745,259 B2, however, the plurality of first terminals and the plurality of second terminals are provided separately from the plurality of electrodes in each layer portion. This is one factor that increases the cost of the layered chip package.